The present invention relates to the field of semiconductor industry and, in particular, to a method of patterning noble metals for use in semiconductor devices such as capacitors.
As the overall dimensions of semiconductor devices continue to decrease, the demand for devices which can be patterned with high-resolution continues to increase. The need for smaller surface area available for components, such as capacitors or transistors, along with the requirement to maintain high-reliability electrical connections, have led researchers in the semiconductor field to seek new materials for such components.
For example, promising candidates for the upper electrode materials for capacitor electrodes in integrated circuit (IC) memory structures include the eight noble metals (platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), rhodium (Rh), osmium (Os), silver (Ag) and gold (Au)), as well as their oxides (for example, ruthenium oxide (RuO2), iridium oxide (IrO2) or osmium oxide (OsO2), among others). The above-mentioned noble metals, of which platinum (Pt) is the most common, are all physically and chemically similar. They are also rather stable, or capable of forming conductive oxides (so the capacitance remains unchanged) in oxidizing, reducing, or inert atmospheres at high temperatures. These metals are also resistant to hydrogen damage, and do not affect the dielectric polarization after annealing at high temperatures.
Recently, particular attention has been accorded to platinum (Pt) mainly because platinum has a very low reactivity and is inert to oxidation, thus preventing oxidation of electrodes which would further decrease the capacitance of storage capacitors. Platinum also has a leakage current lower than that of other electrode materials, for example ruthenium oxide or polysilicon, as well as a high electrical conductivity. Further, platinum is known to have a notably high work function. The work function is an important feature of a DRAM electrode material and, when quantified, it denotes the energy required to remove one electron from the metal. Advanced DRAM cells are characterized by a dominant leakage mechanism, known as the Schottky emission from metal into the dielectric, so that metals, like platinum, with high work function produce less leakage.
The use of platinum as the material of choice for upper capacitor electrodes poses, however, significant problems. One of them arises from the difficulty of etching and/or polishing of platinum and the corresponding need to precisely etch the platinum into the shape of the desired capacitor electrode. The etching process, which is repeated many times in the formation of IC chips, typically employs at least one chemical etchant which reacts with, and removes, the film or layer that is etched. Noble metals, such as platinum, however, are not highly reactive with such chemical etchants and, consequently, noble metals require specialized etching methods and/or highly-reactive chemical etchants.
Two methods are currently used for platinum etching. The first method is an isotropic etching, such as wet etching with aqua regia (mix ratio of concentrated hydrochloric acid: concentrated nitric acid: water=3:1:4), that offers a very low grade of precision. Consequently, such wet etching is not accurate enough for the fine pattern processing, rendering it difficult to perform submicron patterning of platinum electrodes.
The second method is an anisotropic etching, such as the ion beam etching process, under which ions, such as argon, generated by a magnetically confined RF or DC plasma bombard an exposed platinum surface. While the ion etching process is used to define and form high resolution patterns from a blanket platinum layer, this process is typically not selective to many masking materials as well as to the layers underlying the platinum layer. Further, the ion etching process removes most materials at about the same rate, making control of process very difficult.
A further problem with the anisotropic etching of noble metals is that, during the etching process, the photoresist material, which typically masks the noble metal layer, is also etched at a substantial rate, along with the noble metal. This causes the sides of the photoresist mask to shrink and, as a result, the underlying features which were intended to be masked are etched beyond their intended critical dimension. As a consequence, capacitor electrodes, for example, are spaced further apart than desired. This is turn affects the device density on the integrated circuit, which in turn decreases the number of chips to be fabricated on a single wafer.
Accordingly, there is a need for an improved method of patterning of noble metals, such as platinum, during the formation of IC components, such as capacitors or transistors. There is also a need for high-resolution patterning of a noble metal layer during the formation of an upper capacitor electrode, as well as a method for increasing processing accuracy in etching such noble metal.
The present invention provides a method for the selective removal of portions of a noble metal layer employed in the formation of various semiconductor devices, such as capacitors, as well as a method for increasing processing accuracy in etching such noble metals.
In an exemplary embodiment, a layer of noble metal, which will form an upper electrode of a capacitor, is first formed over a dielectric layer. A mask layer is then deposited over the noble metal layer. The mask layer is then patterned to leave a portion of the noble metal layer exposed. The portion of the exposed noble metal is subsequently converted to its silicide, the noble metal silicide is then etched and the insulating layer is removed, leaving the noble metal layer patterned in a conventional upper electrode of an IC capacitor. In a preferred embodiment, platinum (Pt) is used for the upper electrode.
Additional advantages of the present invention will be more apparent from the detailed description and accompanying drawings, which illustrate preferred embodiments of the invention.